1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and, more particularly, to a transistor capable of improving the refresh characteristics of an associated cell in a dynamic random access memory (DRAM), which has a highly integrated structure including a group of cells, and a method for manufacturing the transistor.
2. Description of the Related Art
A DRAM device is well known as a memory device to store data and to allow the stored date to be subsequently read out when the reading of the data is required. This DRAM device is composed of a group of cells each consisting of a capacitor to store data, that is, charge, and a transistor to perform a switching operation to discharge the charge stored in the capacitor.
The data storage of the DRAM device means that charge is accumulated in the capacitors of the DRAM device. Ideally, the charge stored in the capacitors does not disappear. However, recently-developed memory devices have a tendency to have a reduced design rule, so that they have a reduced channel length between a source and a drain in each transistor. As a result, an increase in threshold voltage or an increase in the amount of leakage current at junction regions may occur. For this reason, the data stored in the capacitors may be lost. Also, the refresh characteristics to re-charge the lost charge may be degraded.
In order to prevent such a degradation in refresh characteristics, ion implantation for control of channel threshold voltage may be additionally performed under the condition in which the junction region where each capacitor is joined with a contact, that is, a storage node, is partially shielded during the channel ion implantation process. In this case, however, an abrupt increase in the ion concentration of channel regions occurs, thereby causing a degradation in refresh characteristics.
Hereinafter, the problems incurred in conventional methods of manufacturing the transistors of a semiconductor device will be described with reference to the annexed drawings.
FIGS. 1A and 1B are schematic sectional views respectively illustrating sequential processing steps of a conventional method for manufacturing transistors.
Although not shown, various required ion implantation processes, that is, ion implantation processes for formation of wells, field stop, punch stop and control of channel threshold voltage, are first performed for a silicon substrate 10.
Thereafter, as shown in FIG. 1A, a gate oxide film 20 and a gate polysilicon layer (not shown) are deposited over the silicon substrate 10, and are then subjected to a selective photolithography process to form gate electrodes 30. Subsequently, an insulating material is deposited over the entire upper surface of the substrate 10 formed with the gate electrodes 30, and is then selectively etched to form gate spacers 40 made of the insulating material at respective side walls of the gate electrodes.
Using the gate spacers 40 as an ion implantation mask, an impurity ion implantation process is then carried out for the silicon substrate 10 to form junction regions 50 for formation of cell junction regions.
Thereafter, as shown in FIG. 1B, a photoresist film pattern 60 is formed on the upper surface of the silicon substrate 10 to expose only portions of the upper surface of the silicon substrate 10 respectively corresponding to regions where junctions to contact bit lines, to be subsequently formed, are to be formed as bit line nodes, respectively. Channel threshold ion implantation is then performed. Thus, an asymmetrical junction structure is formed.
FIG. 2 is a schematic view illustrating a simulated electric field distribution of transistors manufactured in accordance with the above-mentioned conventional method. Referring to FIG. 2, it can be seen that the transistors exhibit a threshold voltage Vt of about 1.7E13V and a maximum electric field intensity of about 0.58 MV/cm. That is, it can be seen that a high electric field intensity is exhibited at junction regions.
Thus, when an additional ion implantation process is performed only for the junctions to contact the bit lines, that is, the bit line nodes, in accordance with the conventional method, the impurity concentration of the channel regions is abnormally increased due to the reduced design rule of the DRAM device to be manufactured through the conventional method. As a result, the doping profile established between the channel and the junction is rendered to be sharp, so that an increase in electric field intensity occurs, thereby causing a degradation in refresh characteristics.